1. Field of the Invention
The present invention relates to a liquid crystal display device, and in particular, relates to a liquid crystal display device into which video signals outputted from a personal computer or the like are inputted, and which displays the signals.
2. Description of Related Art
Conventionally, in this type of liquid crystal display device, the video signals which are to be displayed and which are outputted by a personal computer or the like differ from video signals in televisions or the like, in that these video signals are not completely continuously outputted, but are signals in which a fixed potential is maintained for each pixel; furthermore, in the corresponding liquid crystal display device itself, it is not the case that the video signal of one scanning line is continuously displayed, but rather a function is provided in which a video signal sampled pixel by pixel is displayed. This sampling function is provided in the liquid crystal display device; the video signal inputted from a personal computer or the like is displayed after being subjected to sampling within the liquid crystal display device. In the case in which the point at which the video signal is sampled within the liquid crystal display device is not the timing at which a fixed potential of the pixels is maintained, but rather the timing at which the pixels are switched, the following problems occur.
That is to say, there is a problem in that, because sampling of the inputted video signal is conducted at the point at which the potential changes, a constant sampling potential is not obtainable in the set up period or the hold period required in the sampling circuit, and the sampling potential becomes unstable. Furthermore, a situation is created in which, as a result of the influence of jitter in the sampling clock, pre-change pixel data may be sampled in a certain frame, while in the subsequent frame, post-change pixel data may be sampled. As a result of these phenomena, the edges of images in the liquid crystal display seem to flicker and the display quality of the images declines markedly. Accordingly, in such liquid crystal display devices, in order to ameliorate the decline in image quality by means of optimizing the sampling point, a circuit which regulates the phase of the sampling clock becomes necessary.
FIG. 5 is a block diagram showing the structure of the essential parts of a conventional liquid crystal display device in which the adjustment of the sampling clock phase referred to above is performed by the user of the liquid crystal display device while observing the display screen. As shown in FIG. 5, this conventional example is provided with: PLL circuit 1, which creates and outputs a clock PCLK which is phase synchronized with a horizontal synchronizing signal; a phase adjusting circuit 2, which includes a phase adjusting switch 51 and a delay circuit 52, and which adjusts the phase of clock PCLK and outputs a clock SCLK; a sampling pixel data sampling circuit 3, into which a video signal is inputted, and which outputs sampling data via sampling clock SCLK; a liquid crystal drive circuit 4, into which a vertical synchronizing signal and the horizontal synchronizing signal are inputted, and which generates and outputs a liquid crystal display control signal; a liquid crystal panel 5, which displays the video signals which have been video processed; and a video signal processing circuit 6, which processes the sampling data. Normally, a dot clock is not outputted from a personal computer or the like; only a synchronizing signal is outputted. Accordingly, in this type of liquid crystal display device, in order to conduct the sampling of the video signal, a PLL circuit 1 which generates a clock PCLK which is synchronized with the horizontal synchronizing signal is necessary, and this is provided as one of the essential structural elements above.
In FIG. 5, PLL circuit 1 receives the input of the horizontal synchronizing signal, and a clock PCLK which is phase synchronized with the horizontal synchronizing signal is generated and inputted into delay circuit 52. In delay circuit 52, as a result of the manipulation of an operator conducted while viewing the display screen, the delay adjusted signal outputted from phase adjusting switch 51 is received, the phase delay amount of the clock PCLK is controlled and adjusted, and the phase adjusted sampling clock SCLK is outputted and this is inputted into pixel data sampling circuit 3. In pixel data sampling circuit 3, sampling clock SCLK is inputted, and via this sampling clock SCLK, the video signals R/G/B inputted from the personal computer are subjected to sampling. The sampling data output of pixel data sampling circuit 3 is inputted into video processing circuit 6, processing including gamma correction, polarity reversal, and the like is conducted, liquid crystal drive data are generated, these are inputted into liquid crystal panel 5, and display is conducted via the liquid crystal display control signal outputted from liquid crystal drive circuit 4. The liquid crystal display control signal receives the input of the vertical synchronizing signal and the horizontal synchronizing signal and is generated in liquid crystal drive circuit 4, and is inputted into liquid crystal panel 6.
Next, FIG. 6 shows a block diagram of the structure of a different conventional phase adjusting circuit, disclosed in Japanese Patent Application, First Publication, No. Hei 7-219485. As shown in FIG. 6, this phase adjusting circuit comprises: an adjustment initiation switch 66; a controller 63 which accepts as inputs a horizontal synchronizing signal, an operation initiation signal outputted from adjustment initiation switch 66, and a clock PCLK, and outputs a delay adjusting signal; a delay circuit 61, which accepts as inputs the delay adjusting signal and the clock PCLK, and generates and outputs a sampling clock SCLK; an A/D converter 62, which accepts as inputs the sampling clock SCLK, a video signal, and the delay adjusting signal, and subjects the video signal to A/D conversion and outputs this; a memory 65, which accepts as inputs the A/D converted output of the A/D converter 62 and the delay adjusting signal, and which stores the A/D converted output; and a comparator circuit 64, which compares the A/D converted output of the A/D converter 62 and the output of memory 65, and transmits the results of this comparison to controller 63.
In FIG. 6, the video signal inputted from a personal computer or the like is synchronized with sampling clock SCLK and subjected to sampling in A/D converter 62, and is also converted to a digital signal. The prespecified pixel data of a certain frame subjected to sampling in A/D converter 62 are temporarily stored in memory 65. The pixel data stored in memory 65 are compared in comparator circuit 64 with the pixel data corresponding to the same pixel in the subsequent frame, and any difference between these data is detected. In the case in which there was a difference in the results of the comparison, the phase of the sampling clock SCLK is determined to be inappropriate, and via the control function of controller 63, the delay amount in delay circuit 61 is controlled and adjusted, and a comparison of the sampling data is again conducted over a number of frames, and this is repeated until the results of the comparison are in agreement and no difference is generated. In the case of such agreement, the phase of the sampling clock SCLK is determined to be appropriate, and via the control function of controller 63, the delay amount of delay circuit 61 is fixed. The phase adjustment in this conventional example is only initiated when the adjustment initiation switch 66 is placed in the ON position by the operator; the controller 63 receives as an input the operation initiation signal outputted from adjustment initiation switch 66, and the control function of controller 63 commences, and after this, all operations are conducted automatically.
FIG. 7 is a block diagram showing the structure of another conventional phase adjusting circuit, which was disclosed in Japanese Patent Application, First Publication, No. Hei 5-199483. As shown in FIG. 7, this phase adjusting circuit is provided with an edge detecting circuit 71, which detects and outputs the beginning edge of the video signal, and a synchronizing signal 72, which accepts as inputs a clock PCLK and the edge detection output of the edge detecting circuit 71, and which generates and outputs a sampling clock SCLK.
In FIG. 7, in edge detecting circuit 71, the edge of the video signal inputted from a personal computer or the like is detected, and a set pulse is outputted at a timing delayed by a prespecified period from the timing of this edge, and this set pulse is inputted into synchronizing circuit 72. In synchronizing circuit 72, the set pulse is accepted as input, the frequency of the clock PCLK synchronized with the set pulse is N-divided, and a sampling clock SCLK is generated and outputted. By means of this, a sampling clock is obtained which is synchronized with the edge of the inputted video signal. In this case, as the division value N becomes larger in synchronizing circuit 72, it is possible to restrict the phase error to a smaller value, and N is commonly set to a value of 8 or more. Furthermore, by means of delaying the timing of the set pulse by a prespecified amount from the edge, the phase difference between the video signal and the sampling clock SCLK is fixed and optimized, and thereby the adjustment of the sampling point may be realized automatically.
In the conventional liquid crystal display devices described above, in the case of the conventional example shown in FIG. 5, the operator manipulates a switch while viewing the display screen, and thereby, the timing adjustment of the sampling clock SCLK is conducted, but there is a disadvantage in that the manipulations of the operator may become complex.
Furthermore, in the conventional phase adjusting circuit shown in FIG. 6, by means of conducting a comparison of the sampling data of the video data corresponding to a certain pixel frame by frame, the timing adjustment of the sampling point with respect to the video signal is conducted; however, in the case of moving images in which the display screen changes frame by frame, the inputted video signal changes with each frame, and a comparison between frame units will never result in agreement, and it is thus impossible to conduct optimal timing adjustment, and this represents a drawback in that the displayed images during adjustment are limited to still images.
In this conventional example, it is not possible to continuously conduct adjustment, so that a switch operation is also necessary in order to initiate adjustment, and this has the additional drawback that this operation is complex, and furthermore, in the timing adjustment, a number of frame intervals are required, so that time is required for the timing adjustment.
Furthermore, in the conventional phase adjusting circuit shown in FIG. 7, the edge of the video signal is detected, and synchronization is conducted with respect to a set pulse which is delayed by a prespecified time from the edge detection signal, and thereby, the timing of the sampling point is adjusted; however, in cases in which, as a result of the personal computer or the like outputting the video signal which is to be displayed, the wave-form of differing video signals becomes disordered as a result of noise or the like originating in ringing or reflection or the like, and this affects the timing of the set pulse delayed by a predetermined period from the edge, it becomes impossible to guarantee the set up time required in the sampling circuit of the pixel data, and the timing of the sampling point is not set to the appropriate timing. Additionally, when the level of the noise or the like arising from ringing or reflection or the like of the video signal is high, edge detection is conducted with respect to the wave form of this noise or the like in the edge detecting circuit, and it becomes impossible to optimally adjust the sampling point.